RISC-V 32-bit Reference Card and Quiz

Quick interactive summary of the RISC-V ISA (RV32I, M, A, F, D, C, Pseudo, Registers)

What is RISC-V 32-bit (RV32)?

RISC-V is an open standard instruction set architecture (ISA) based on reduced instruction set computing (RISC) principles. RV32 is the 32-bit version, supporting 32-bit registers, addresses, and data types. It is widely used in embedded and academic environments for its simplicity and extensibility.

This tutorial covers the basics and lets you interactively explore and test your knowledge!

Instruction Formats

TypeFieldsDescription
R-typeopcode, rd, funct3, rs1, rs2, funct7Register-register operations
I-typeopcode, rd, funct3, rs1, imm[11:0]Immediate, loads, jalr, system
S-typeopcode, imm[4:0], funct3, rs1, rs2, imm[11:5]Stores
B-typeopcode, imm[11], imm[4:1], funct3, rs1, rs2, imm[10:5], imm[12]Branches
U-typeopcode, rd, imm[31:12]LUI, AUIPC
J-typeopcode, rd, imm[20|10:1|11|19:12]JAL

Core Integer Instructions (RV32I)

NameFormatOpcodefunct3Description
ADDR01100110x0rd = rs1 + rs2
SUBR01100110x0rd = rs1 - rs2
XORR01100110x4rd = rs1 ^ rs2
ORR01100110x6rd = rs1 | rs2
ANDR01100110x7rd = rs1 & rs2
SLLR01100110x1rd = rs1 << rs2
SRLR01100110x5rd = rs1 >> rs2 (logical)
SRAR01100110x5rd = rs1 >> rs2 (arith)
SLTR01100110x2rd = (rs1 < rs2)?1:0
SLTUR01100110x3rd = (rs1 < rs2 unsigned)?1:0
ADDII00100110x0rd = rs1 + imm
XORII00100110x4rd = rs1 ^ imm
ORII00100110x6rd = rs1 | imm
ANDII00100110x7rd = rs1 & imm
SLLII00100110x1rd = rs1 << imm[0:4]
SRLII00100110x5rd = rs1 >> imm[0:4] (logical)
SRAII00100110x5rd = rs1 >> imm[0:4] (arith)
SLTII00100110x2rd = (rs1 < imm)?1:0
SLTIUI00100110x3rd = (rs1 < imm unsigned)?1:0
LB/LH/LWI00000110x0/0x1/0x2rd = M[rs1+imm][0:7/15/31]
LBU/LHUI00000110x4/0x5rd = M[rs1+imm][0:7/15] (unsigned)
SB/SH/SWS01000110x0/0x1/0x2M[rs1+imm][0:7/15/31] = rs2
BEQ/BNE/BLT/BGE/BLTU/BGEUB11000110x0/0x1/0x4/0x5/0x6/0x7Conditional branches
JALJ1101111-rd = PC+4; PC += imm
JALRI11001110x0rd = PC+4; PC = rs1+imm
LUIU0110111-rd = imm << 12
AUIPCU0010111-rd = PC + (imm << 12)
ECALL/EBREAKI11100110x0System call / Break

Standard Extensions

RV32M (Multiply/Divide)

RV32A (Atomic)

RV32F/D (Floating Point)

RV32C (Compressed)

Pseudo-Instructions

Register ABI

RegisterABI NameDescription
x0zeroZero constant
x1raReturn address
x2spStack pointer
x3gpGlobal pointer
x4tpThread pointer
x5-x7t0-t2Temporaries
x8s0/fpSaved/frame pointer
x9s1Saved register
x10-x11a0-a1Function args/return values
x12-x17a2-a7Function args
x18-x27s2-s11Saved registers
x28-x31t3-t6Temporaries

Floating Point Registers

Quiz Yourself!

What does the ADD instruction do in RV32?
Which register is the stack pointer?
What is the difference between LW and LB?